1. Field of the Invention
This invention relates generally to electrostatic discharge protection, and, more particularly, to an optically triggered electrostatic discharge protection circuit.
2. Description of the Related Art
Circuits, particularly integrated circuits that are formed on semiconductor wafers, are vulnerable to damage or destruction caused by unexpectedly large surges of power through the circuit. For example, a packaged integrated circuit typically includes numerous bond pads that can be used to electrically couple the integrated circuit to the outside world. However, current from electrostatic discharges, e.g. from lightning strikes or static electricity buildup on a person, can enter the integrated circuit through the bond pads and potentially cause damage to the integrated circuit. Circuit packages therefore typically include electrostatic discharge (ESD) protection circuits that attempt to electrically isolate the bond pad from the integrated circuit in the event of an unexpectedly large power surge. The ESD protection circuit usually directs the current produced by the power surge to ground so that this current does not enter the protected circuit.
FIG. 1 conceptually illustrates a conventional ESD protection circuit 100. In the illustrated embodiment, a bond pad 105 is separated from a circuit by a primary ESD protection element 110, an isolation resistor 115, and a secondary ESD protection element 120. The secondary ESD protection element 120 typically turns on in response to an ESD event to protect the circuit until the primary ESD protection element 110 can turn fully on. The primary ESD protection element 110 shunts most (or all) of the current during the ESD event. However, the primary ESD protection element 110 may not immediately reach a fully on state in response to the start of the ESD event. The secondary ESD protection element 120 may therefore serve to limit the voltage/current until the primary ESD protection element 110 is fully on. Current is pulled from the bond pad through the isolation resistor 115 when the secondary ESD protection element 120 turns on. The current causes a potential drop across the isolation resistor 115 and the primary ESD protection element 110 turns on when this potential drop reaches the triggering voltage of the primary ESD protection element 110.
The conventional ESD protection circuit 100 suffers from a number of drawbacks. For example, problems may occur with setting the proper latching thresholds for a given technology. Furthermore, the additional resistance and/or capacitance associated with the conventional ESD protection circuit 100, and in particular the isolation resistor 115, may limit the range and/or performance of the protected circuit or node.